Mitigating AI Training Power Oscillations: Utility Requirements and In-Rack Power Filtering#

Bo Wen (Microsoft), Xianyong Feng (Microsoft)

• Why: A surprising cross-domain result: synchronized GPU compute/communication phase transitions at cluster scale overlap with sensitive utility-grid frequency bands, creating forced-oscillation and impedance-stability risks — power design is becoming a networking-adjacent constraint on cluster architecture.
• What: A framework connecting grid-side power-transient requirements (power-change and oscillation limits, ramp-rate expectations, synchronized monitoring from utility interconnect down to rack level) with practical in-rack mitigation, including PSU + CBU filtering concepts, frequency-sweep test methods, attenuation analysis, and verification results (from abstract only).
• How: Rack-level buffering (PSU plus CBU) measurably reduces upstream power ripple; measurement and modeling align AI rack power design with utility requirements.
• Where applicable: Relevant to any operator at multi-hundred-MW AI scale interacting with utilities; Microsoft-specific verification data, but the utility constraints are universal for large campuses.