Performance Evaluation of Interconnect Technologies for AI Scale-Up Computing: UAL vs UALoE/SUE vs RoCE#

Speakers: Srihari Vegesna (Upscale AI), Srinivas Gangam (Upscale AI)

• Why: Scale-up interconnect choice (proprietary memory-semantic links vs. Ethernet-based alternatives) is the biggest architectural fork in AI cluster design right now, and head-to-head evaluations with real transfer-size sweeps are rare.
• What: A comparative evaluation of Ultra Accelerator Link (UAL), Ethernet-based UALoE/SUE, and RoCE for AI-optimized, memory-semantic XPU-to-XPU transfer. Reported result: UAL wins on small transfers via deterministic latency and transaction-based load balancing; Ethernet protocols suffer variable latency and inefficient small-packet handling. (from abstract only)
• How: Transaction-level load balancing, DMA thread efficiency, and bandwidth utilization measured across small- and large-transfer scenarios for memory-semantic workloads.
• Where applicable: Applicable to scale-up (in-pod) AI systems rather than scale-out fabrics; findings favor link-level memory semantics, which constrains how far Ethernet-based scale-up can currently go. Note the authors' UAL bias is visible in the framing — read the methodology carefully.