OCP Global Summit 2025#

Core#

CSIG: Congestion Signaling in the AI Era#

Abstract Recording

Speakers: Abhiram Ravi (Google), Jai Kumar (Broadcom)

• Why: Millisecond-duration AI bursts expose the limits of ECN-only congestion signals; this is the mechanism-level answer, and it's deployed, standardized, and multi-vendor — the trifecta for judging whether something is real.
• What: Congestion Signaling (CSIG) — line-rate, always-on telemetry in application context, plus fine-grained per-packet congestion feedback that captures both the state and the location of the bottleneck on a path. Includes Google production results showing improvements to congestion control and load balancing. (from abstract only)
• How: Sub-millisecond-granularity switch traffic measurements embedded in signaling, feeding both congestion control responsiveness and load-balancing quality; being standardized under UEC with multiple switch vendors supporting it.
• Where applicable: Deployed at Google production scale — Google-specific results, but the mechanism is being standardized at UEC and supported by multiple switch vendors, so it is broadly relevant to anyone designing AI fabric feedback loops.

Performance Evaluation of Interconnect Technologies for AI Scale-Up Computing: UAL vs UALoE/SUE vs RoCE#

Abstract Recording

Speakers: Srihari Vegesna (Upscale AI), Srinivas Gangam (Upscale AI)

• Why: Scale-up interconnect choice (proprietary memory-semantic links vs. Ethernet-based alternatives) is the biggest architectural fork in AI cluster design right now, and head-to-head evaluations with real transfer-size sweeps are rare.
• What: A comparative evaluation of Ultra Accelerator Link (UAL), Ethernet-based UALoE/SUE, and RoCE for AI-optimized, memory-semantic XPU-to-XPU transfer. Reported result: UAL wins on small transfers via deterministic latency and transaction-based load balancing; Ethernet protocols suffer variable latency and inefficient small-packet handling. (from abstract only)
• How: Transaction-level load balancing, DMA thread efficiency, and bandwidth utilization measured across small- and large-transfer scenarios for memory-semantic workloads.
• Where applicable: Applicable to scale-up (in-pod) AI systems rather than scale-out fabrics; findings favor link-level memory semantics, which constrains how far Ethernet-based scale-up can currently go. Note the authors' UAL bias is visible in the framing — read the methodology carefully.

Enabling Technologies for Next Generation Large Scale AI Backend Networking#

Abstract Recording

Speakers: Guohan Lu (Microsoft), Mehak Mahajan (Broadcom)

• Why: Complements the SRv6 talk with the rest of Microsoft's next-gen backend feature set — high-frequency streaming telemetry and "trimming" — plus an honest read on whether SAI/SONiC can actually support hyperscale AI backends yet.
• What: Microsoft's next-generation backend AI network architecture as clusters grew from tens of thousands to hundreds of thousands of GPUs: SRv6, High-Frequency Streaming Telemetry (HFST), and trimming, with the driving factors and implementation details, and an assessment of SAI/SONiC readiness. (from abstract only)
• How: Backend networks get distinct requirements from traditional DCs — low latency, high throughput, proactive fault detection — which push traffic engineering and telemetry to first-class features; the talk covers how each is implemented.
• Where applicable: Microsoft-scale AI backend, co-presented with Broadcom — some content will track specific silicon capabilities via SAI. The SAI/SONiC readiness discussion is directly relevant to anyone on the open-networking stack.

eCore: Architecture and Whitebox Evolution of Alibaba's Service-oriented DCI network#

Abstract Recording

Speakers: Dennis Cai (Alibaba), Manish Mukherjee (Cisco)

• Why: DC/WAN interconnect is core to the PM's remit, and Alibaba's eCore is one of the few publicly detailed whitebox DCI architectures — modular, service-aware, and with claimed measurable impact.
• What: Alibaba's Data Center Interconnect network built on a modular whitebox-based architecture with service-aware traffic forwarding powered by SRv6, co-presented with Cisco on design philosophy, deployment challenges, measurable impact, and the roadmap. (from abstract only)
• How: Service-aware SRv6 forwarding over a whitebox chassis/architecture rather than traditional DCI routers; details of the custom whitebox solutions are promised in the talk.
• Where applicable: Alibaba-specific production DCI, but the pattern (whitebox + SRv6 service awareness for DC-to-DC) is the direction hyperscalers are generally taking. Watch for the "measurable impact" claims being quantified in the room rather than the abstract.

The Path to Zero Flap: Reinventing Optical Reliability for Scalable AI Clusters presented by Credo#

Abstract Recording

Speakers: Stephen Manley (Oracle), Bill Brennan (Credo)

• Why: The headline number — commodity pluggable optics at up to 30,000 FITs — is the reliability crisis in AI fabrics in one figure, and a single flapping link can kill a training run. This also launches a new OCP optical-reliability workstream, so it's a standards signal, not just a vendor demo.
• What: A joint Oracle/Credo "Zero Flap" optical solution aiming to eliminate unplanned link flaps in million-GPU backend networks, combining host- and line-side telemetry, in-band messaging, event logging, and predictive analytics. Architecture is being contributed to OCP to seed a new workstream; initial results are promised. (from abstract only)
• How: Correlate host-side and line-side telemetry with in-band messaging between link endpoints, log events, and predict failures before they become flaps — moving reliability from reactive BER monitoring to prediction.
• Where applicable: Jointly developed for Oracle's AI infrastructure with Credo silicon — partly vendor-specific — but the contribution to OCP is intended to make the framework open and general. The FIT figure for commodity pluggables is an industry-wide baseline.

OCP Optical Circuit Switching Subproject Update#

Abstract Recording

Speakers: Brian O'Connor (Google), Richard Yu (Google)

• Why: Google's OCS deployment reshaped the fabric-topology conversation (static Clos vs. reconfigurable); this new OCP subproject is about standardizing and open-sourcing the OCS control stack — a direction signal for physical DC topology design.
• What: Status of the OCS subproject (formed June) within the OCP Networking project: developing open software standards and a fully open software stack for optical circuit switching, targeting high bandwidth, low latency, and energy efficiency for AI/ML and HPC. (from abstract only)
• How: Standardization plus an open-source software stack so that OCS from multiple manufacturers can interoperate and be orchestrated — the abstract is a project-status announcement, so expect scope and roadmap rather than deep technical results.
• Where applicable: Aimed at general data center and AI/ML networking, not Google-specific; this is early-stage standards work, useful mainly as a where-is-this-heading read.

Evaluation of CPO Performance and Pluggable Optics Health for Reliable AI Infrastructure#

Abstract Recording

Speakers: Siamak Amiralizadeh (Meta), VIRAL LOWALEKAR (Meta)

• Why: CPO is the biggest pending change in DC physical-layer architecture, and the honest questions are reliability, availability, and serviceability — exactly what Meta claims to test here, with multi-month methodologies rather than lab anecdotes.
• What: Meta's comprehensive evaluation of co-packaged optics against current pluggable transceivers, plus their multi-month reliability testing methodology for both current and next-generation optical technologies (including CPO) to enable robust link-failure detection and long-term optical reliability. (from abstract only)
• How: Power/cost optimization assessment of CPO (optics integrated on-ASIC) against improving pluggables, combined with systematic multi-month reliability testing across Meta's diverse transceiver fleet supporting AI/ML connectivity.
• Where applicable: Meta datacenter fleet and AI/ML connectivity — the results should be interpretable industry-wide since CPO tradeoffs are physical, but the failure-detection tooling is Meta's own.

Development Challenges and Next-Generation Opportunities for Linear Drive Pluggable Optics (LPO) and Linear Receive Optics (LRO)#

Abstract Recording

Speakers: Nan Ge (Meta Platforms), Amin Yekani (Meta)

• Why: LPO/LRO is the pragmatic alternative to CPO for cutting optics power — no DSP on the link — and this is a development-experience talk with lessons learned and feasibility studies, not a vendor roadmap deck.
• What: Meta's optical interconnect architecture around 200G/L transceivers for front-end and back-end AI networks, a comparison of photonics technologies at 200G/L, desired diagnostic features for large-scale training, and development experience with LPO and LRO including feasibility studies. (from abstract only)
• How: Removing (LPO) or halving (LRO) the DSP to reduce power and cost, then working through the consequences: technical challenges, system compatibility with switch ASICs, and diagnostics — which are notoriously weaker without a DSP to measure the link.
• Where applicable: Meta's 200G/L architecture, but LPO/LRO tradeoffs (power vs. diagnosability vs. reach) are general to any 800G/1.6T network. The "desired diagnostic features" list is useful input for anyone specifying optics requirements.

Disaggregated Leaf-Spine Architecture for Next-gen Azure T2 Network#

Abstract Recording

Speakers: Kamini Santhanagopalan (Broadcom), Rita Hui (Microsoft)

• Why: SONiC Disaggregated Chassis is the most consequential open-networking architecture idea of the last few years — replacing chassis boxes with pizza-box fabrics — and this is a concrete Microsoft/Broadcom spine-layer deployment with named silicon.
• What: A fully disaggregated spine-layer solution built from pizza boxes on xgs and dnx chipsets: TH5-512 silicon in the lower-disagg-T2 and Q3D (Jericho-based) in the upper-disagg-T2, replacing monolithic chassis for the Azure T2 spine. (from abstract only)
• How: SONiC Disaggregated Chassis separates hardware and software components with clean hardware abstractions so the spine scales past a single chassis's physical limits; the talk covers the design and the advantages of the model.
• Where applicable: Azure-specific and explicitly Broadcom-silicon-specific (TH5-512 and Q3D) — the architecture pattern (pizza-box disagg spine under SONiC) is general, but the implementation details are tied to this chipset pairing.

Driving Innovation in Network Infrastructure: Key Advances from the Sonic Routing Workgroup#

Abstract Recording

Speakers: Patrice Brissette (Cisco Systems Inc.), Eddie Ruan (Alibaba)

• Why: This is the "where is the open routing stack actually heading" session — BGP/datapath internals on the PM's list — covering real SONiC community work with named contributors from Cisco and Alibaba rather than a single vendor's roadmap.
• What: A year-in-review of the SONiC Routing workgroup: SRv6 development and the Phoenixwing initiative, VxLAN Multi-Homing progress, upgrading Free Range Routing (FRR) to 10.x, RIB/FIB separation architecture, and the effect of the new mid-week workgroup meetings. (from abstract only)
• How: Contributor-led engineering status and next steps for each initiative; the abstract names the projects but not their technical detail, so value is in the status/roadmap clarity.
• Where applicable: General to SONiC deployments; RIB/FIB separation and FRR 10.x are directly relevant to anyone running or building on SONiC control planes.

Unifying P4 with eBPF and DPDK via XDP2#

Abstract Recording

Speakers: Tom Herbert (XDPnet)

• Why: The PM's eBPF/datapath interest makes this directly relevant: XDP2 attacks the fragmentation between P4 (switch ASICs), eBPF/XDP (hosts), and DPDK (userspace fast paths) — a real pain point for anyone building programmable network functions across targets.
• What: XDP2, a unified programming model that takes the best of P4, XDP/eBPF, and DPDK so users can program in their language of choice and run the same code unmodified across a variety of targets. (from abstract only)
• How: A target-agnostic model that lets datapath code be written once and compiled to switch ASICs, kernel eBPF, and userspace/DPDK execution — the abstract does not describe the compiler/IR mechanism, so expect that in the talk.
• Where applicable: General-purpose infrastructure programming; Tom Herbert's track record (XDP, XDPnet) lends credibility. Early-stage effort — the abstract is a vision plus workshop pointer rather than results, so judge maturity from the live demo.

Accurate Cable Length Measurement for Optimized Data Center Networking#

Abstract Recording

Speakers: Jasmeet Bagga (Facebook), Mehak Mahajan (Broadcom)

• Why: Cabling is a named core interest, and this pairs a Meta production deployment (operational benefits, real use cases) with a Broadcom technical deep dive including the SAI attributes that make it deployable — an unusually complete story for a plumbing topic.
• What: Inferring physical cable length via silicon-driven link delay measurement, with Meta presenting real-world deployment experience and observed operational benefits, and Broadcom detailing the delay-measurement methodology and the SAI attributes/APIs that support it. (from abstract only)
• How: High-precision link delay measurement from switch silicon, exposed through SAI, used both for accurate cable-length inventory and for performance monitoring.
• Where applicable: Broadcom silicon with the SAI delay-measurement attributes (silicon-dependent), deployed at Meta — the use cases (cable inventory accuracy, layout validation, latency anomaly detection) apply to any large DC.

Adjacent#

New Strategic Initiative: Open Cluster Designs for AI#

Abstract Recording

Speakers: Lowell Lamb (Broadcom), Loren Staley (Celestica)

• Why: Not deep tech, but a formation announcement for OCP standardizing pod and cluster topologies — directly relevant to anyone whose physical DC designs must interoperate, and a place to influence reference designs early.
• What: A new OCP Strategic Initiative for standardized designs of Open Pod Groups and Open Clusters: scale-up and scale-out networks in scope, physical and logical topology in scope, modularity as a fundamental objective, and management built on OCP management specifications. (from abstract only)
• How: Reusing existing OCP platform and component contributions wherever possible to build best-practice reference cluster designs rather than new spec work from scratch.
• Where applicable: Industry-wide reference-design effort, not operator-specific; value now is scope and participation, concrete designs come later.

Methodology and Observation of Congestion Control Impact on MoE Training Job Completion Time#

Abstract Recording

Speakers: Alex Bortok (Keysight)

• Why: A methodology talk rather than a vendor pitch: how to emulate an AI fabric and measure the effect of congestion-control and load-balancing schemes on MoE training JCT — useful for anyone building test harnesses before spending production GPUs on it.
• What: An emulation technique and methodology to quantify AI network fabric performance for Mixture-of-Experts training, comparing the impact of different congestion control and load-balancing schemes. (from abstract only)
• How: Lab emulation of GPU-cluster fabrics running MoE workloads, with JCT as the outcome metric across congestion control / load balancing configurations.
• Where applicable: Test-lab methodology (Keysight tooling implied) — vendor-presented, so expect the tool to feature, but the emulation-vs-production calibration questions are worth taking into the room.

Wildcard#

Firefly: Scalable, Ultra-Accurate Clock Synchronization for Datacenters#

Abstract Recording

Speakers: Yuliang Li (Google)

• Why: Sub-10ns device-to-device sync is two orders of magnitude past what PTP practice delivers, and the technique — consensus on a random overlay rather than a spanning tree — is a genuinely different way to solve time in a fabric. Cloud financial exchanges are the driver, but precise time increasingly matters for telemetry correlation and distributed debugging.
• What: A software-driven datacenter clock sync system achieving sub-10ns device-to-device and ≤1µs device-to-UTC accuracy in a 248-machine Clos network, resilient to time server failure and unstable clocks. (from abstract only)
• How: A distributed consensus algorithm over a random overlay graph converges devices to a common time with gradual hardware-clock adjustments; "layered synchronization" decouples internal (device-to-device) from external (UTC) sync so external jitter doesn't disturb internal consistency.
• Where applicable: Software-only, demonstrated on a 248-machine Clos network — no special hardware claimed. Google research system; results are from that testbed, so hyperscale behavior is inferred rather than shown.

XASM: A Foundation to Program the X2 With P4#

Abstract Recording

Speakers: Fabian Ruffy (XSight Labs), Vladimir Gurevich (XSight Labs)

• Why: The P4 ecosystem has been pipeline-model-bound since Tofino; if a new switch architecture (X2) breaks that model, it forces the P4 language itself to evolve. Watching a language's assumptions get stress-tested by new silicon is valuable even if the PM never programs an X2.
• What: The X2 architecture contrasted with the traditional P4 pipeline model (Tofino-style), how XASM maps P4 constructs onto X2, where current P4 cannot express X2's capabilities, and candidate paths for evolving the P4 language. (from abstract only)
• How: XASM serves as a programming foundation/abstraction layer between P4 and the X2 hardware, with concrete mapping examples and a candid limitations discussion.
• Where applicable: XSight Labs X2 silicon-specific, but the language-evolution conclusions (what P4 must gain) affect the whole programmable-datapath community.

Themes#

• AI backend fabrics own the agenda. Nearly every core session bends to one problem: building reliable, non-blocking Ethernet fabrics for 100K+ GPU clusters — SRv6 path control (Microsoft), capacity-aware adaptive routing (Meta), UEC 1.0, scale-up vs. scale-out interconnect comparisons. BGP+ECMP is being explicitly declared insufficient, and the replacements (SRv6, adaptive spray, transaction-level load balancing) are the live design frontier.
• Optics reliability is the new bottleneck. 30,000-FIT pluggables (Zero Flap), ML-based SerDes failure prediction (INSPECT), multi-month CPO/LPO reliability testing (Meta), and silicon-based cable length measurement all attack the same realization: at AI scale, link failures — not bandwidth — dominate downtime and job restarts.
• Telemetry becomes a first-class fabric feature. CSIG (congestion location signaling), High-Frequency Streaming Telemetry, host/line-side optical telemetry, and SerDes telemetry form a pattern: in-band, line-rate, application-context measurement feeding congestion control, load balancing, and predictive maintenance.
• The open software stack is absorbing routing complexity. SONiC's Routing workgroup (SRv6, VxLAN multi-homing, FRR 10.x, RIB/FIB separation), Meta's SAI/FBOSS evolution, disaggregated-chassis spines in Azure, and a new open OCS software stack show open networking moving from "box replacement" to owning hard routing and fabric-management problems.
• Ethernet is contesting every tier. UALoE/SUE and RoCE press into scale-up against memory-semantic links, SRv6 Ethernet wins the backend at Microsoft and Meta, and eCore brings Ethernet whiteboxes to DCI — while the UAL-vs-Ethernet evaluation shows exactly where Ethernet still loses (small transfers, latency determinism).
• Hardware identity and attestation are maturing fast. Caliptra's DICE/DPE identity chain and SPDM's authorization and post-quantum work signal that the RoT layer — the physical anchor for everything the PM cares about in identity — is converging on open, standardized designs with a PQC migration already scheduled.