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Co-Engineering Grace CPU Platforms for Hyperscale#

GTC 2026 digest Program Adjacent pick San Jose · 16–19 March 2026

Abstract Talk page Slides Recording

Shobhit Kanaujia, Abhishek Dhanotia (Meta), Ian Finder (NVIDIA) — Talk, Tuesday, March 17

  • Why: End-to-end platform co-engineering at one of the world's largest fleets — performance-per-watt and rack-density context that shapes DC planning even though it isn't a networking talk per se.
  • What: How Meta and NVIDIA co-engineer Grace CPU-based platforms for Meta's diverse fleet (training, inference, web services, ranking, caching, analytics, video processing), improving performance per watt, rack density, and fleet efficiency. (from abstract only)
  • How: Joint work across silicon, platform design, and infrastructure integration; abstract doesn't detail the mechanisms or quantify the gains.
  • Where applicable: Meta-specific fleet at hyperscale; the co-engineering process observations generalize, the results are fleet-specific.