P4OVN: Offloading OVN to Intel IPU for Intel Developer Cloud#

Speakers: Junho Suh, Intel, Inc. (from abstract only)

Why: A production DPU/IPU offload of OVN — not a demo — running in Intel Developer Cloud, and one of the few concrete data points on where SmartNIC-based virtual networking is actually deployed at service scale.

What: A hardware/software co-design: a hardware flow cache implemented in P4 on the IPU's programmable packet processing engine handles L2/L3 forwarding and connection tracking, while the IPU's compute tiles run OVS for stateful processing (ACL, NAT, LB). Covers deployment and operation for distributed virtual routers and distributed/centralized NAT gateways, plus OVN central, engineered to meet IDC scale requirements.

How: Partitioning by statefulness — stateless fast-path classification in programmable hardware, stateful exceptions on the IPU's ARM compute — with an explicit discussion of open-sourcing the work and encompassing other vendors' solutions.

Where applicable: Intel IPU-specific today; interesting as a template for the "programmable-P4 fast path + OVS slow path on DPU compute" pattern that parallels NVIDIA's DOCA DPIF and Marvell's approach.