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Harnessing Marvell Accelerators with OVS Hardware Offload for Accelerated Network Performance#

Open vSwitch and OVN 2024 Fall Conference (Prague) digest Program Adjacent pick Prague · 20–21 November 2024

Abstract Slides Recording

Speakers: Harman Kalra, Jerin Jacob Kollanukkaran, Marvell

Play the recording: Harnessing Marvell Accelerators with OVS Hardware Offload for Accelerated Network Performance

Why: Concrete DPU silicon detail (Octeon CN10K) from a vendor other than NVIDIA — useful for anyone comparing offload platforms.

What: An "ovs-offload-engine" alongside OVS that offloads OVS-classified flows into the CN10K's parser/CAM hardware: NIX (controller/DMA), NPC (parser forming MCAM keys, 16K entries), NPA (packet memory pointers), CPT (inline IPsec by intercepting strongSwan SA/SP policies via DPDK rte_security), conntrack-offload compensation, virtio integration up to 100 Gbps, and flow actions (RSS, VLAN strip/insert, mirroring, multicast).

How: Initial/exception packets processed by OVS, then installed into CAM so subsequent packets are matched in hardware; future work includes hierarchical scheduling/shaping up to five levels, LSO, and checksum generation.

Where applicable: Marvell Octeon CN10K-specific; the extracted slides are diagram-heavy and number-light, so treat the performance claims as vendor-stated.