Feeding the AI Factory: The Role of DPU/IPUs in AI Infrastructure - Tina Tsou, Board Chair, LF Edge; Rajalaxmi Angadi, Senior Engineering Manager, Intel & Moderated by Paul Pindell, F5 Networks#

Speakers: Tina Tsou (LF Edge / InfiniEdge AI TSC), Rajalaxmi Angadi (Intel), Paul Pindell (F5 Networks)

• Why: Positions the DPU question the industry is actually arguing about: at 800G+ AI-fabric scale, the bottleneck shifts from GPU compute to data movement, storage I/O, and infrastructure overhead — and the panel's through-line is whether OPI can keep heterogeneous DPU/IPU fleets from fragmenting into per-vendor silos.
• What: A panel discussion on offloading virtual networking, NVMe-oF storage access for KV caches, security enforcement, and telemetry to DPUs/IPUs to reclaim host CPU/GPU cycles, enforce hardware-isolated security air gaps, and improve AI job completion times in multi-tenant clusters — with emphasis on OPI's role in preventing vendor lock-in via standardized gRPC APIs, gNMI telemetry, and the community DPU Operator as unified northbound abstractions. (from abstract only)
• How: Panel format — no single technique to evaluate, but the framing (one open AI-factory blueprint over heterogeneous silicon, DPU as the multi-tenancy security boundary) is a useful synthesis of where hyperscalers and cloud providers are converging.
• Where applicable: Relevant to multi-tenant AI cluster operators and cloud providers; the OPI abstractions it references are real upstream work (DPU Operator, gNMI, gRPC) but the session itself is discussion, not evaluation. Skew toward Intel/NVIDIA-era 800G assumptions.