SyncWise: Error-Aware Time Synchronization for Reconfigurable Data Center Networks#

Yiming Lei (MPI for Informatics), Jialong Li (Shenzhen University of Advanced Technology), Zhengqing Liu (Imperial College London), Raj Joshi (Harvard), Yiting Xia (MPI)

• Why: As reconfigurable DCNs (OCS-based) shrink circuit durations to microseconds/sub-microseconds, accurate time sync becomes the correctness backbone of the whole fabric — and this paper shows the problem was previously unformalized. A foundational gap-fill for the reconfigurable-fabric subfield.
• What: The first time-synchronization protocol designed specifically for reconfigurable DCNs. It formalizes the RDCN sync problem, builds an RDCN-specific error model, and achieves provably optimal sync — sub-10 ns maximum sync error, well beyond what the most accurate traditional-DC protocols achieve.
• How: Uses the RDCN error model (sources of error specific to dynamic optical circuits) to guide "wise" selection of sync parents — choosing the peers whose sync exchanges will be least corrupted by circuit reconfiguration dynamics.
• Where applicable: Specific to OCS-based reconfigurable DCNs; prototyped on an Intel Tofino2 + OCS testbed with large-scale simulations backing the testbed numbers. Not relevant to static packet fabrics, but core reading for anyone evaluating express-loop/circuit-switched designs.