Building Modern and Scalable DC Fabrics#

Alperen Akpinar — Nokia

• Why: A useful map of how a major vendor is restructuring its DC portfolio around AI fabrics — backend fabrics, lossless/QoS, and DC gateways/DCI — plus an automation stack (EDA) that operators can actually try without a license.
• What: An evolution framing (STP/VLANs → VPLS → EVPN/VXLAN → SRv6/uSID, 10M → 800G+) anchored on the scale challenge: AI is redefining "large DC" from ~30 MW (2013) to 100K–1M-GPU "AI factories". The concrete architecture: two-tier topologies for 1K–16K GPU clusters, multi-plane topologies for 100K+; 800G AI backend fabrics on 7220 IXR-H5 / 7250 IXR; dynamic load balancing and RDMA-aware (Q-pair) hashing; DCQCN with PFC/ECN; real-time congestion telemetry; backend multi-tenancy segmentation; DC gateways with 800G ZR+ coherent DCI and 4×400G FlexE bundles; Event-Driven Automation (EDA) on SR Linux with a model-driven NDK and Kubernetes-based foundation.
• How: The transferable pattern is the tiering of designs by cluster size (two-tier vs multi-plane) and the coupling of backend fabric features (DLB, Q-pair hashing, congestion indicators) with an intent/event-driven automation layer rather than box-by-box config.
• Where applicable: The portfolio specifics are Nokia-only (IXR platforms, EDA) — this is a vendor solution overview, not a neutral paper. The sizing/topology patterns and the "try-eda" unlicensed playground (make try-eda, no registration) are the broadly applicable bits.