The CXL Fabric End-Game: Bandwidth Realities and Networked Memory for AI Scale#

PJ Waskiewicz

Why: A useful corrective to the "CXL memory is just a far NUMA node" framing that keeps showing up in AI infrastructure planning.

What: An argument that bandwidth, not latency, is the binding constraint on network-attached CXL memory pools, and a sketch of what memory-coherent cluster execution would actually require.

How: CXL link bandwidth can be orders of magnitude below native multi-channel DDR, so the bandwidth-to-core ratio changes the economics of scaling models across pooled memory even though the latency is manageable; CXL 2.0 has only just introduced hardware memory pooling. The talk outlines the required work across switching infrastructure, firmware, and Linux networking and memory subsystems. (From abstract only.)

Where applicable: Forward-looking ("moonshot" track) — treat as a constraint map for CXL-based memory disaggregation plans, not a deployment guide.