Keynote: Beyond the Chip: The Unprecedented Infrastructure Demands of AI and HPC#

Bill Conrades, Chris Stewart, Michael Balasko — AHEAD

• Why: The most concrete "facility-to-fabric" framing of AI datacenter buildouts at this meeting. For anyone whose remit includes physical DC design, this maps how power and cooling constraints now dictate network architecture choices — the limiting factors are no longer transistors but power delivery, cooling, and system-level architecture.
• What: A structured survey of AI/HPC infrastructure: rack density evolution from air-cooled (<10-15kW) through hybrid/liquid (30-80kW+) to liquid-everything (100-150kW+); a cooling technology ladder (perimeter CRAC → containment → rear-door heat exchange → direct-to-chip → immersion) with capacity bands per technology; and the networking backbone — AI backend (East/West, 1:1 oversubscription) vs frontend (North/South) reference architecture, rail-optimized topology for AllReduce collectives, and a useful comparative table of Ethernet variants (standard ECMP → enhanced ECMP+advanced LB → scheduled packet-spraying/VOQ → Ultra Ethernet) with honest cluster-size and losslessness trade-offs.
• How: Built around AHEAD's own 10MW specialized integration facility case study (permitting timelines, hybrid air + facility-water cooling, D2C and RDHx plans) plus a Gartner impact radar for timing investments (DLC and AI Ethernet fabrics rated "act now"; in-package microfluidics, HVDC, 800V distribution on longer horizons). Includes physical-layer detail: MPO/xPC/breakout planning, 800G still riding 100G SerDes with 200G SerDes emerging, DC bus bar and ORv3/MGX rack standards.
• Where applicable: Broadly applicable planning guidance for AI-era facilities, though presented by a systems integrator (with Cisco-credited diagrams and NVIDIA NVL72 examples), so expect consultative framing rather than an operator postmortem. The cooling-capacity numbers and Ethernet-variant table transfer to any AI DC program.