From Datacenter to AI Center, building the networks that build AI#

Tyler Conrad — Arista Networks

• Why: The best single "orientation map" for engineers moving from general-compute DC design to AI backends. Vendor-presented, but dense with concrete numbers you can reuse in capacity planning, and refreshingly honest about failure rates.
• What: A design guide across topology (single-box vs 2-tier vs 3-tier with GPU-count ceilings per form factor; rail-isolated vs rail-optimized vs fat-tree; multi-plane scaling by port-speed fan-out — 1x800G/2x400G/4x200G), subscription ratios (target 1:1 or better), optics economics, load balancing and congestion control (ECMP hashing vs RDMA-aware static hashing vs DLB vs packet spraying vs SRv6 steering), RoCEv2 mechanics (DCQCN, PFC victim flows, ECN/ECT tuning, a concrete QoS queue design with CNP in SP queues), and segmentation options from VLANs to VRFs to SRv6 uSID.
• How: Prescriptive with arithmetic: for a hypothetical 100k-GPU back-end, 257,904 links and 515,808 optics; at 2.3M-hour MTBF that is one optic failure roughly every 4.45 hours — about five per day. LPO optics (no DSP, DSP moved into switch silicon) claimed at ~0.5x power, ~0.7x cost, ~0.01x latency. Includes a common-failure checklist (QoS mismatch, dirty fiber, FEC/autoneg mismatch, MMU tuning) that mirrors what real AI-cluster escalations look like.
• Where applicable: Greenfield AI back-end builds; the talk's own takeaway is that back-end reuse of existing gear is unlikely and power/heat is usually the first constraint. Arista perspective throughout, so silicon-specific framing (radix/speed tables) should be re-derived for other vendors.