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AI Backend: Deploying SRv6 uSID and SONiC for Deterministic Load Balancing#

NANOG 96 digest Program Core pick 2–4 February 2026

Pablo Camarillo — Cisco Systems; Rita Hui — Microsoft

Play the recording: AI Backend: Deploying SRv6 uSID and SONiC for Deterministic Load Balancing

  • Why: The AI backend load-balancing problem is the defining fabric issue of this cycle: synchronized, bursty, low-entropy training flows destroy ECMP hash assumptions, and congestion/loss stalls GPU collectives. This is a production answer from one of the world's largest AI infrastructures, not a whitepaper.
  • What: Microsoft's deployment of SRv6 uSID strict source routing in the AI backend for deterministic, conflict-free traffic placement, implemented in SONiC. The deck grounds it in real cost data (Llama3 406B: 6k GPUs, 54 days, 419 unplanned interruptions; a single job crash loses 15-30 minutes of compute since the last checkpoint) and includes a taxonomy of every LB approach attempted — switch-based (flowlet, adaptive routing, packet spray) and NIC-based (oblivious spray, entropy recycling) — and why probabilistic entropy-value switching can't guarantee a new path.
  • How: GPU/NIC controls the full end-to-end path by encoding a uSID list in the packet header; on congestion or failure the NIC swaps SIDs and the path changes immediately with no state propagation through the fabric. The backend runs as a statically provisioned fabric with static SIDs and static routes — no dynamic routing, avoiding the ~120,000 packets lost when an ECMP group updates after a link flap on a fully utilized 400G link. Also covers tenancy/slicing via SRv6 policy without DPU cycles, and the SONiC SRv6 ecosystem (uN/uDT functions, FRR, contributors incl. Microsoft, Alibaba, Broadcom, Nvidia). The Alibaba eCore SRv6 DCI design is shown as the scale-across analog.
  • Where applicable: Microsoft-scale AI backends on SONiC whiteboxes; requires SRv6-capable NICs/DPUs and merchant silicon (Broadcom/G400-class). The "deterministic path placement" idea is also feeding UEC standardization, so the architecture is transferable even where the exact stack is not. Co-presented by Cisco's SRv6 lead — expect enthusiasm — but the operational data and failure math are the substance.