200 GbE network processing with 100 W - or "can I make a chip for that?"#

Philipp Keydel (Synogate)

• Why: An accessible explanation of why hardware offload wins for network processing at scale, plus an introduction to Gatery — an open-source C++ hardware construction library that lowers the barrier to custom silicon/FPGA development. Relevant to the PM's interest in the hardware/software boundary of network processing.
• What: A talk covering: why chips beat CPUs for networking (determinism, energy efficiency, compute density, longevity), why the industry needs more chips (network evolution outpacing CPU improvements per Nielsen's Law), what can be achieved today (200 GbE stateful throughput at 240M new connections/s, 16B concurrent connections, 35W), and why making circuits is still hard (verbose tools, insufficient designers, 30-year-stagnant tooling). Introduces Gatery as an open-source (LGPL) C++ hardware construction library for rapid prototyping and iteration.
• How: Gatery provides a modern C++-based alternative to VHDL/Verilog for RTL design, enabling agile development with reuse of tested components, automation of boilerplate, and seamless integration into traditional toolchains. Target-hardware-agnostic. The talk covers the full flow: requirements → engineering → RTL design → testing/verification → synthesis → tape-out/FPGA.
• Where applicable: Teams evaluating hardware offload for TCP processing, cybersecurity, or traffic shaping. Also relevant to anyone curious about custom silicon or FPGA development with modern tooling. Vendor-agnostic (open-source framework); the specific 200G/35W figures are Synogate's product results.