SwitchNIC: Tightly-Coupled Heterogeneous Platform to Accelerate Network Functions#

Yiran Lei (Carnegie Mellon University); Francisco Chamiça Pereira (INESC-ID/IST Lisboa); Arvind Krishnamurthy (University of Washington); Justine Sherry (Carnegie Mellon University)

• Why: The PISA-switch + general-purpose-server hybrid ("best of both worlds") keeps failing on one problem: keeping distributed state consistent across the two platforms without wrecking latency. This paper attacks exactly that, and it is the kind of result that shapes the next generation of hybrid middlebox designs.
• What: A tightly-coupled architecture guaranteeing consistent shared state between a Tofino switch and co-located general-purpose processors, with 6µs P99 packet latency, 5.2× better energy efficiency, and 6.4× better processing latency than server-based systems — which the authors note cannot fully/correctly support shared state between platforms (from abstract only).
• How: A novel "on-path" state replication protocol, with latency tightened by running the general-purpose processing on locally-integrated ARM cores rather than a separate x86 server. Prototype: Tofino + Ethernet-attached ARM-based SmartNICs.
• Where applicable: Network functions needing both line-rate PISA processing and complex/stateful general-purpose logic. Constrained to hardware you can pair closely (switch + ARM SmartNICs in the same box/chassis); Intel Tofino's future availability is a known ecosystem risk for PISA-based designs generally.