Building AI/ML Fabrics at Hyperscale: Architecture Evolutions, Challenges, Open Standards, Performance Characterization and Validation on Cisco SiliconOne-based Platforms. - BRKMSI-2014#

Masiuddin Mohammed (Cisco), Evan Knipp (Cisco)

• Why: The single densest architectural map of where AI-scale DC fabrics are going — cluster size, topology generations, and DCI constraints are exactly the design questions a physical-networking PM needs answered.
• What: A trace of AI fabric evolution from 4K/16K-GPU leaf-spine, to 64K-GPU Disaggregated Scheduled Fabric (DSF) two-tier with super-spines, to >200K-GPU three-tier scale-out, plus multi-DC DCI interconnect; paired with a benchmarking methodology for validating these fabrics (from abstract only).
• How: Addresses scale-out concerns (fat flows, ECMP polarization, asymmetric failures, fault resilience) separately from scale-up concerns (~8x per-accelerator bandwidth for tensor-parallel, e.g. NVL72), and DCI demands of high-speed buffering and encryption over ~100 km / 1 ms RTT. Validation is done in production-like environments using open, standards-aligned test practices to minimize test drift.
• Where applicable: Cisco-specific (Silicon One platforms) and hyperscaler-derived, but the topology taxonomy, failure-mode catalog, and benchmark methodology generalize to any large AI fabric build.