Evolution of Transport Protocols#

Geoff Huston — APNIC

• Why: Connects end-host congestion control to switch-silicon design constraints — buffer sizing math, on-chip memory tradeoffs, ECN, and BBR. Rare to see transport theory and switching hardware economics in one talk; directly relevant to physical DC networking and lossless-fabric thinking.
• What: Why TCP session speeds have stalled in the tens of Gbps while optical transport heads to multi-terabit. The progression: Reno AIMD → CUBIC (fast capacity reaction but extended queue-formation phases and bufferbloat exacerbation) → BBR (pacing plus periodic RTT-based capacity probes every 8^th RTT with 25% rate excursions; does not change its bandwidth estimate on loss). Buffer theory: single-flow sizing = BW·RTT; N desynchronized flows need BW·RTT/√N (Appenzeller/McKeown/Keslassy); with paced senders the residual requirement drops to O(log W). The punchline for switching: on-chip memory is only ~16–64MB, memory/memory-control consumes 20–60% of switch die area, and memory speed isn't scaling with transmission — so future capacity gains mandate smaller buffers, which demands paced, queue-sensitive senders (ECN or delay probing). ECN deployment remains sparse despite being the natural router-side queue-onset signal.
• How: Control-law mechanics (ACK pacing, loss vs. delay probing, queue drain timing), buffer-sizing derivations, and a candid closing: "we don't know all that much about fine-grained behaviour of large-scale high-capacity switching systems… the Internet still contains important unsolved problems."
• Where applicable: Broadly applicable fundamentals, vendor-neutral. The buffer-size and chip-memory sections directly inform DC switch selection and capacity planning; relevant context (not a treatment of) RDMA/lossless fabrics, which sidestep TCP control loops entirely.